CMOS inverter and logic gates

Timing concepts (delay, setup, hold)

Power, performance, and area basics

Binary, octal, hexadecimal

Signed vs unsigned arithmetic

Fixed-point representation

Overflow and saturation

Combinational logic design

Sequential logic design

Latches vs flip-flops

Synchronous design principles

Linux file system

Shell commands

Makefiles basics

Simulation environment setup

Verilog syntax and constructs

Blocking vs non-blocking assignments

Always blocks

Module hierarchy

Logic data type

always_comb, always_ff

Interfaces and modports

Parameterized design

Muxes, encoders, decoders

Counters and registers

Pipelining techniques

Reset strategies

Moore vs Mealy FSMs

State encoding techniques

FSM coding styles

Debugging FSM issues

Synthesizable coding rules

Avoiding latches and glitches

Clock and reset handling

Reusable RTL design

Testbench basics

Self-checking testbenches

Functional coverage concepts

Debug using waveform viewers

RTL to gate-level flow

Timing, area, power trade-offs

Common synthesis issues

Reading synthesis reports

Setup and hold analysis

Clock uncertainty and skew

Path exceptions

Timing-aware RTL coding

CDC problem types

Synchronizer flops

Async FIFO design

CDC verification concepts

Reset synchronization

Async vs sync resets

Power-up sequencing

Reset-related bugs

Power consumption in RTL

Clock gating techniques

Isolation and retention concepts

Introduction to UPF

Clock definitions

Input/output delays

False paths and multicycle paths

Writing RTL-friendly constraints

Scan concepts

Test-friendly RTL coding

Memory BIST basics

DFT guidelines for designers

Bus protocols overview (AXI, AHB, APB)

IP integration

Address decoding

Interrupt handling

RTL linting rules

Common RTL violations

CDC/RDC tool reports

Clean RTL sign-off checklist

Complete RTL block design

Coding, simulation, linting

Synthesis and timing check

Interview-focused explanation